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INTEGRATED CIRCUITS
80C451/83C451/87C451 80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
Product specification Supersedes data of 1998 Jan 19 IC20 Data Handbook 1998 May 01
Philips Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
DESCRIPTION
The Philips 8XC451 is an I/O expanded single-chip microcontroller fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes latch-up sensitivity. The 8XC451 (includes the 80C451, 87C451 and 83C451) is a functional extension of the 87C51 microcontroller with three additional I/O ports and four I/O control lines for a total of 68 pins. Four control lines associated with port 6 facilitate high-speed asynchronous I/O functions. The 8XC451 includes a 4k x 8 ROM (83C451) EPROM (87C451), a 128 x 8 RAM, 56 I/O, two 16-bit timer/counters, a five source, two priority level, nested interrupt structure, a serial I/O port for either a full duplex UART, I/O expansion, or multi-processor communications, and on-chip oscillator and clock circuits. The 80C451 ROMless version includes all of the 83C451 features except the on-board 4k x 8 ROM. The 87C451 has 4k of EPROM on-chip as program memory and is otherwise identical to the 83C451. The 8XC451 has two software selectable modes of reduced activity for further power reduction; idle mode and power-down mode. Idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. Power-down mode freezes the oscillator, causing all other chip functions to be inoperative while maintaining the RAM contents.
PIN CONFIGURATION
9 1 61
10
60
LCC
26
44
27 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Function EA/VPP P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC P4.7 P4.6 P4.5 P4.4 P4.3 Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Function P4.2 P4.1 P4.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD P5.0 P5.1 P5.2
43 Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function P5.3 P5.4 P5.5 P5.6 P5.7 XTAL2 XTAL1 VSS ODS IDS BFLAG AFLAG P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 PSEN ALE/PROG
FEATURES
* 80C51 based architecture * Seven 8-bit I/O ports * Port 6 features:
- Eight data pins - Four control pins - Direct MPU bus interface - Parallel printer interface
SU00084A
* On the microcontroller:
- 4k x 8 ROM (83C451) 4k x 8 EPROM (87C451) ROMless version (80C451) - 128 x 8 RAM - Two 16-bit counter/timers - Two external interrupts
* External memory addressing capability
- 64k ROM and 64k RAM
* Low power consumption:
- Normal operation: less than 24mA at 5V, 12MHz - Idle mode - Power-down mode
1998 May 01
2
853-0830 19327
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7 P4.0-P4.7 P5.0-5.7
PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 4 DRIVERS
PORT 5 DRIVERS
PORT 2 LATCH
PORT 4 LATCH
PORT 5 LATCH
4K x 8 ROM/EPROM
B REGISTER
ACC
STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
BUFFER ALU PCON TL1 PSW SBUF IE IP INTERRUPT, SERIAL PORT AND TIMER BLOCKS PC INCREMENTER SCON TH0 TMOD TL0 TCON TH1
PROGRAM COUNTER PSEN ALE/PROG EAVPP RST PD TIMING AND CONTROL INSTRUCTION REGISTER
DPTR
PORT 1 LATCH
PORT 6 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 PORT 6 DRIVERS PORT 6 CONTROL/STATUS PORT 3 DRIVERS
P1.0-P1.7
P6.0-P6.7
IDS ODS BFLAG AFLAG
P3.0-P3.7
SU00086
1998 May 01
3
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
ORDERING INFORMATION
ROMless SC80C451CCA68 SC80C451CGA68 ROM SC83C451CCA68 SC83C451CGA68 EPROM1 SC87C451CCA68 SC87C451CGA68 OTP OTP TEMPERATURE RANGE C AND PACKAGE 0 to +70, Plastic Leaded Chip Carrier, 0 to +70, Plastic Leaded Chip Carrier FREQ MHz 3.5 to 12 3.5 to 16 DRAWING NUMBER SOT188-3 SOT188-3
NOTE: 1. OTP = One Time Programmable
LOGIC SYMBOL
VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS
XTAL2
SECONDARY FUNCTIONS
RST EA/VPP PSEN ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD
PORT 3
PORT 2
PORT 1
ADDRESS BUS
PORT 6 CONTROL
ODS IDS BFLAG AFLAG
PORT 6
PORT 5
PORT 4
SU00085
1998 May 01
4
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
PIN DESCRIPTION
MNEMONIC VSS VCC P0.0-0.7 PIN NO. 54 18 17-10 TYPE I I I/O NAME AND FUNCTION Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order address bus during accesses to external memory. External pull-ups are required during program verification. Port 0 can sink/source eight LS TTL inputs. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address bytes during access to external memory and receives the high-order address bits and control signals during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Port 4: Port 4 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 4 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 5: Port 5 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 5 can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the functions listed below: ODS: Output data strobe IDS: Input data strobe BFLAG: Bidirectional I/O pin with internal pull-ups AFLAG: Bidirectional I/O pin with internal pull-ups Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during an external data memory access, at which time one ALE is skipped. ALE can sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse during EPROM programming. Program Store Enable: The read strobe to external program memory. PSEN is activated twice each machine cycle during fetches from external program memory. However, when executing out of external program memory, two activations of PSEN are skipped during each access to external program memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low during programming. Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU executes out of internal program memory, unless the program counter exceeds 0FFFH. When EA is held low, the CPU executes out of external program memory. EA must never be allowed to float. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external oscillator when an external oscillator is used. Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used.
P1.0-P1.7
27-34
I/O
P2.0-P2.7
2-9
I/O
P3.0-P3.7
36-43
I/O
36 37 38 39 40 41 42 43 P4.0-P4.7 P5.0-P5.7 P6.0-P6.7 26-19 44-51 59-66
I O I I I I O O I/O I/O I/O
ODS IDS BFLAG AFLAG RST ALE/PROG
55 56 57 58 35 68
I I I/O I/O I I/O
PSEN
67
O
EA/VPP
1
I
XTAL1 XTAL2
53 52
I O
1998 May 01
5
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
I/O Port Structure
The 8XC451 has a total of seven parallel I/O ports. The first four ports, P0 through P3, are identical in function to those present on the 80C51 family. The added ports 4 and 5 are identical in function to port 1; that is, they are standard quasi-bidirectional ports with no alternate functions and the standard output drive characteristics. Port 6 is a specialized 8-bit bidirectional I/O port with internal pullups.
Processor Bus Interface
Port 6 allows the use of an 8XC451 as an element on a microprocessor type bus. The host processor could be a general purpose MPU or the data bus of a microcontroller like the 8XC451 itself. Setting up the 8XC451 as a processor bus interface allows single or multiple microcontrollers to be used on a bus as flexible peripheral processing elements. Applications can include: keyboard scanners, serial I/O controllers, servo controllers, etc. On reset, port 6 is programmed correctly (that is, Special Function registers CSR and P6) for use as a bus interface. This prevents the interface from disrupting data on the bus of a host processor during power-up.
Ports 4 and 5
Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4 is an 8-bit port. Port 4 and port 5 pins with ones written to them, are pulled high by the internal pull-ups, and in that state can be used as inputs. Port 4 and 5 are addressed at the special function register addresses shown in Table 1.
Standard Quasi-bidirectional I/O Port
To use port 6 as a common I/O port, all of the control pins should be tied to ground. On hardware reset, bits 2-7 of the CSR are set to one. With the control pins grounded, the port's operation and electrical characteristics will be identical to port 1 on the 80C51. No further software initialization is required.
Port 6
Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups (see Figure 1). This special port can sink/source three LS TTL inputs and drive CMOS inputs without external pullups. The flexibility of this port facilitates high-speed parallel data communications. This port can be used as a standard I/O port, or in strobed modes of operation in conjunction with four special control lines: ODS, IDS, AFLAG, and BFLAG. Port 6 operating modes are controlled by the port 6 control status register (CSR). Port 6 and the CSR are addressed at the special function register addresses shown in Table 1. The following four control pins are used in conjunction with port 6: ODS - Output data strobe (Active Low) for port 6. ODS can be programmed to control the port 6 output drivers and the output buffer full flag (OBF), or to clear only the OBF flag bit in the CSR (output-always mode). ODS is active low for output driver control. the OBF flag can be programmed to be cleared on the negative or positive edge of ODS. IDS - Input data strobe (Active Low) for port 6. IDS is used to control the port 6 input latch and input buffer full flag (IBF) bit in the CSR. The input data latch can be programmed to be transparent when IDS is low and latched on the positive transition of IDS, or to latch only on the positive transition of IDS. Correspondingly, the IBF flag is set on the negative or positive transition of IDS. BFLAG - BFLAG is a bidirectional I/O pin which can be programmed to be an output, set high or low under program control, or to output the state of the input buffer full flag. BFLAG can also be programmed to input an enable signal for port 6. When BFLAG is used as an enable input, port 6 output drivers are in the high-impedance state, and the input latch does not respond to the IDS strobe when BFLAG is high. Both features are enabled when BFLAG is low. This feature facilitates the use of the SC8XC451 in bused multiprocessor systems. AFLAG - AFLAG is a bidirectional I/O pin which can be programmed to be an output set high or low under program control, or to output the state of the output buffer full flag. AFLAG can also be programmed to be an input which selects whether the contents of the output buffer, or the contents of the port 6 control status register will output on port 6. This feature grants complete port 6 status to external devices. Port 6 can be used in a number of different ways to facilitate data communication. It can be used as a processor bus interface, as a standard quasi-bidirectional I/O port, or as a parallel printer port (either polled or interrupt driven).
Parallel Printer Port
The 8XC451 has the capacity to permit all of the intelligent features of a common printer to be handled by a single chip. The features of port 6 allow a parallel port to be designed with only line driving and receiving chips required as additional hardware. The onboard UART allows RS232 interfacing with only level shifting chips added. The 8-bit parallel ports 0 to 6 are ample to drive onboard control functions, even when ports are used for external memory access, interrupts, and other functions. The RAM addressing ability of ports 0 to 2 can be used to address up to 64k bytes of a hardware buffer/spooler. In addition, either end of a parallel interface can be implemented using port 6, and the interfaces can be interrupt driven or polled in either case. For more detailed information on port 6 usage, refer to the application notes entitled "80C451 Operation of Port 6" and "256k Centronics Printer Buffer Using the SC87C451 Microcontroller."
CONTROL STATUS REGISTER
The control status register (CSR) establishes the mode of operation for port 6 and indicates the current status of port 6 I/O registers. All control status register bits can be read and written by the CPU, except bits 0 and 1, which are read only. Reset writes ones to bits 2 through 7, and writes zeros to bits 0 and 1 (see Table 3). CSR.0 Input Buffer Full Flag (IBF) (Read Only) - The IBF bit is set to a logic 1 when port 6 data is loaded into the input buffer under control of IDS. This can occur on the negative or positive edge of IDS, as determined by CSR.2 IBF is cleared when the CPU reads the input buffer register. CSR.1 Output Buffer Full Flag (OBF) (Read Only) - The OBF flag is set to a logic 1 when the CPU writes to the port 6 output data buffer. OBF is cleared by the positive or negative edge of ODS, as determined by CSR.3. CSR.2 IDS Mode Select (IDSM) - When CSR.2 = 0, a low-to-high transition on the IDS pin sets the IBF flag. The Port 6 input buffer is loaded on the IDS positive edge. When CSR.2 = 1, a high-to-low transition on the IDS pin sets the IBF flag. Port 6 input buffer is transparent when IDS is low, and latched when IDS is high.
1998 May 01
6
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
CSR.3 Output Buffer Full Flag Clear Mode (OBFC) - When CSR.3 = 1, the positive edge of the ODS input clears the OBF flag. When CSR.3 = 0, the negative edge of the ODS input clears the OBF flag. CSR.4, CSR.5 AFLAG Mode Select (MA0, MA1) - Bits 4 and 5 select the mode of operation for the AFLAG pin as follows: MA1 0 0 1 1 MA0 0 1 0 1 AFLAG Function Logic 0 output Logic 1 output OBF flag output (CSR.1) Select (SEL) input mode
CSR.6, CSR.7 BFLAG Mode Select (MB0, MB1) - Bits 6 and 7 select the mode operation as follows: MB1 MB0 0 0 0 1 1 0 1 1 BFLAG Function Logic 0 output Logic 1 output IBF flag output (CSR.0) Port enable (PE)
In the port enable mode, IDS and ODS inputs are disabled when BFLAG input is high. When the BFLAG input is low, the port is enabled for I/O.
SPECIAL FUNCTION REGISTER ADDRESSES
The SFRs are identical to those of the standard 80C51 with the exception of four registers that have been added to allow control of the three additional I/O ports P4, P5, and P6. The additional registers are P4, P5, P6, and CSR. Registers P4, P5, and P6 function as port latches for ports 4, 5, and 6, respectively. These registers operate identically to those for ports 0 through 3 of the 80C51.
The select (SEL) input mode is used to determine whether the port 6 data register or the control status register is output on port 6. When the select feature is enabled, the AFLAG input controls the source of port 6 output data. A logic 0 on AFLAG input selects the port 6 data register, and a logic 1 on AFLAG input selects the control status register.
Table 1. Special Function Register Addresses
REGISTER ADDRESS NAME Port 4 Port 5 Port 6 data Port 6 control status SYMBOL P4 P5 P6 CSR ADDRESS C0 C8 D8 E8 MSB C7 CF DF EF C6 CE DE EE C5 CD DD ED C4 CC DC EC C3 CB DB EB C2 CA DA EA C1 C9 D9 E9 BIT ADDRESS LSB C0 C8 D8 E8
AFLAG
BFLAG ODS
PORT 6
IDS
BFLAG/ODS MODE (CSR.6/.7)
OUTPUT DRIVERS
INPUT BUFFER (P6 READ)
IDS MODE
AFLAG MODE (CSR.4/.5)
INPUT BUFFER FULL (CSR.0) MUX EDGE/LEVEL SELECT (CSR.2)
OUTPUT BUFFER FULL (CSR.1) CONTROL/STATUS REGISTER (CSR) OUTPUT BUFFER (P6 WRITE)
INTERNAL BUS
SU00087
Figure 1. Port 6 Block Diagram
1998 May 01
7
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
Table 2.
SYMBOL ACC* B*
8XC451 Special Function Registers
DESCRIPTION Accumulator B register DIRECT ADDRESS E0H F0H BIT NAMES AND ADDRESSES MSB E7 F7 EF E6 F6 EE MB0 E5 F5 ED MA1 E4 F4 EC MA0 E3 F3 EB OBFC E2 F2 EA IDSM E1 F1 E9 OBF LSB E0 F0 E8 IBF FCH RESET VALUE 00H 00H
CSR*# DPTR DPH DPL
Port 6 command/status Data pointer (2 bytes) Data pointer high Data pointer low
E8H
MB1
83H 82H BF BE - BD - BC PS BB PT1 BA PX1 B9 PT0 B8 PX0
00H 00H
IP*
Interrupt priority
B8H
-
xxx00000B
AF IE* P0* P1* P2* P3* P4*# P5*# P6*# Interrupt enable Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 A8H 80H 90H A0H B0H C0H C8H D8H EA 87 97 A7 B7 C7 CF DF
AE - B6 96 A6 B6 C6 CE DE
AD - 85 95 A5 B5 C5 CD DD
AC ES 84 94 A4 B4 C4 CC DC
AB ET1 83 93 A3 B3 C3 CB DB
AA EX1 82 92 A2 B2 C2 CA DA
A9 ET0 81 91 A1 B1 C1 C9 D9
A8 EX0 80 90 A0 B0 C0 C8 D8 0xx00000B FFH FFH FFH FFH FFH FFH FFH
PCON
Power control
87H
SMOD
-
-
-
GF1
GF0
PD
IDL
0xxx0000B
D7 PSW* SBUF Program status word Serial data buffer D0H 99H 9F SCON* SP Serial port control Stack pointer 98H 81H 8F TCON* Timer/counter control 88H TF1 SM0 CY
D6 AC
D5 F0
D4 RS1
D3 RS0
D2 OV
D1 -
D0 P 00H xxxxxxxxB
9E SM1
9D SM2
9C REN
9B TB8
9A RB8
99 TI
98 RI 00H 07H
8E TR1
8D TF0
8C TR0
8B IE1
8A IT1
89 IE0
88 IT0 00H
TMOD TH0 TH1 TL0 TL1
Timer/counter mode Timer 0 high byte Timer 1 high byte Timer 0 low byte Timer 1 low byte
89H 8CH 8DH 8AH 8BH
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H 00H 00H 00H 00H
* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs.
1998 May 01
8
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
Table 3. Control Status Register (CSR)
Bit 7 MB1 Bit 6 MB0 Bit 5 MA1 Bit 4 MA0 Bit 3 OBFC Output Buffer Flag Clear Mode 0 = Negative edge of ODS 1 = Positive edge o ODS Bit 2 IDSM Input Data Strobe Mode 0 = Positive edge of IDS 1 = Low level of IDS Bit 1 OBF Output Buffer Flag Full 0 = Output data buffer empty 1 = Output data buffer full Bit 0 IBF Input Buffer Flag Full 0 = Input data buffer empty 1 = Input data buffer full
BFLAG Mode Select
AFLAG Mode Select
0/0 = Logic 0 output* 0/1 = Logic 1 output* 1/0 = IBF output 1/1 = PE input (0 = Select) (1 = Disable I/O)
0/0 = Logic 0 output* 0/1 = Logic 1 output* 1/0 = OBF output 1/1 = SEL input (0 = Select) (1 = Control/status)
NOTE: * Output-always mode: MB1 = 0, MA1 = 1, and MA0 = 0. In this mode, port 6 is always enabled for output. ODS only clears the OBF flag.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on any other pin to VSS Power dissipation (based on package heat transfer limitations, not device power consumption) RATING 0 to +70 -65 to +150 -0.5 to +6.5 1.5 UNIT C C V W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
1998 May 01
9
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
DC ELECTRICAL CHARACTERISTICS1
Tamb = 0C to +70C, VCC = 5V 10%, VSS = 0V (87C451, 83C451, 80C451) TEST SYMBOL VIL VIL1 VIH VIH1 VOL VOL1 VOH PARAMETER Input low voltage; except EA Input low voltage to EA Input high voltage; except XTAL1, RST Input high voltage; XTAL1, RST Output low voltage; ports 1, 2, 3, 4, 5, 6 Output low voltage; port 0, ALE, PSEN Output high voltage; ports 1, 2, 3, 4, 5, 6 IOL = IOL = 1.6mA2 3.2mA2 2.4 0.75VCC 0.9VCC 2.4 0.75VCC 0.9VCC -50 -650 +10 11.5 1.3 3 50 25 4 50 300 10 CONDITIONS MIN -0.5 0 0.2VCC+0.9 0.7VCC LIMITS TYPICAL1 MAX 0.2VCC-0.1 0.2VCC-0.3 VCC+0.5 VCC+0.5 0.45 0.45 UNIT V V V V V V V V V V V V A A A mA mA A k pF
IOH = -60A, IOH = -25A IOH = -10A IOH = -800A, IOH = -300A IOH = -80A VIN = 0.45V See note 4 VIN = VIL or VIH See note 6
VOH1
Output high voltage (port 0 in external bus mode, ALE, PSEN)3 Logical 0 input current,; ports 1, 2, 3, 4, 5, 6 Logical 1-to-0 transition current; ports 1, 2, 3, 4, 5, 6 Input leakage current; port 0 Power supply current: Active mode @ 12MHz5 Idle mode @ 12MHz5 Power down mode Internal reset pull-down resistor Pin capacitance7
IIL ITL ILI ICC
RRST CIO
NOTES: 1. Typical ratings are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. ICCMAX at other frequencies is given by: Active mode: ICCMAX = 0.94 X FREQ + 13.71 Idle mode: ICCMAX = 0.14 X FREQ +2.31 where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 13. 6. See Figures 14 through 17 for ICC test conditions. 7. CIO applies to ports 1 through 6, AFLAG, BFLAG, XTAL1, XTAL2.
1998 May 01
10
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
AC ELECTRICAL CHARACTERISTICS1
Tamb = 0C to +70C, VCC = 5V 10%, VSS = 0V (87C451, 83C451, 80C451)2 12MHz CLOCK SYMBOL 1/tCLCL FIGURE PARAMETER Oscillator frequency: SC8XC451 SC8XC451 2 2 2 2 2 2 2 2 2 2 2 ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 59 312 10 43 205 145 0 tCLCL-25 5tCLCL-105 10 Speed Versions C G 127 28 48 234 tCLCL-40 3tCLCL-45 3tCLCL-105 MIN MAX VARIABLE CLOCK MIN 3.5 3.5 2tCLCL-40 tCLCL-55 tCLCL-35 4tCLCL-100 MAX 12 16 UNIT MHz MHz ns ns ns ns ns ns ns ns ns ns ns
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH Shift Register tXLXL tQVXH tXHQX tXHDX tXHDV
3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4
RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high
400 400 252 0 97 517 585 200 203 23 33 0 43 123 300
6tCLCL-100 6tCLCL-100 5tCLCL-165 0 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL-50 4tCLCL-130 tCLCL-60 tCLCL-50 0 tCLCL-40 tCLCL+40 3tCLCL+50
ns ns ns ns ns ns ns ns ns ns ns ns ns
5 5 5 5 5
Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
1.0 700 50 0 700
12tCLCL 10tCLCL-133 2tCLCL-117 0 10tCLCL-133
s ns ns ns ns
NOTES: SEE NEXT PAGE
1998 May 01
11
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
AC ELECTRICAL CHARACTERISTICS1 (continued)
Tamb = 0C to +70C, VCC = 5V 10%, VSS = 0V (87C451, 83C451, 80C451)2 12MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX VARIABLE CLOCK MIN MAX UNIT
Port 6 input (input rise and fall times = 5ns) tFLFH tILIH tDVIH tIHDX tIVFV Port 6 output tOLOH tFVDV tOLDV tOHDZ tOVFV tFLDV tOHFH External Clock tCHCX tCLCX tCLCH tCHCL 10 10 10 10 High time Low time Rise time Fall time 20 20 20 20 20 20 20 20 ns ns ns ns 6 7 6 6 6 6 7 ODS width SEL to data out delay ODS to data out delay ODS to data float delay ODS to AFLAG (OBF) delay PE to data out delay ODS to AFLAG (SEL) delay 100 270 85 80 35 100 120 100 3tCLCL+20 85 80 35 100 120 ns ns ns ns ns ns ns 8 8 8 8 9 PE width IDS width Data setup to IDS high or PE high Data hold after IDS high or PE high IDS to BFLAG (IBF) delay 270 270 0 30 130 3tCLCL+20 3tCLCL+20 0 30 130 ns ns ns ns ns
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
1998 May 01
12
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 2. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A0-A15 FROM PCH
SU00007
Figure 3. External Data Memory Read Cycle
1998 May 01
13
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A0-A15 FROM PCH
SU00008
Figure 4. External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 5. Shift Register Mode Timing
1998 May 01
14
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
OBF (AFLAG)
tOVFV
PE (BFLAG)
tOVFV
tOLOH
ODS
tOLDV
PORT 6
tOHDZ
tFLDV
SU00088
Figure 6. Port 6 Output
ODS
tOHFH
SEL (AFLAG)
tFVDV
tFVDV
PORT 6
DATA
CSR
DATA
SU00089
Figure 7. Port 6 Select Mode
tFLFH
PE (BFLAG)
tILIH
IDS
tDVIH
PORT 6
tIHDZ
SU00090
Figure 8. Port 6 Input
IBF (BFLAG)
tIVFV
IDS
tIVFV
SU00091A
Figure 9. IBF Flag Output
1998 May 01
15
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 10. External Clock Drive
VCC-0.5
0.2VCC+0.9 0.2VCC-0.1
0.45V
NOTE: AC inputs during testing are driven at VCC -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
SU00010
Figure 11. AC Testing Input/Output
VLOAD+0.1V VLOAD VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00011
Figure 12. Float Waveform
30
MAX ACTIVE MODE
25
20
ICC mA
15
TYP ACTIVE MODE
10
5
MAX IDLE MODE TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz
FREQ AT XTAL1 VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF THE DEVICE UNDER TEST.
SU00092
Figure 13. ICC vs. FREQ
1998 May 01
16
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 IDS VSS ODS VSS IDS ODS VCC (NC) CLOCK SIGNAL XTAL2 XTAL1 VCC RST P0 EA VCC
VCC ICC
VCC
RST
VCC
SU00093
SU00094
Figure 14. ICC Test Condition, Active Mode All other pins are disconnected
Figure 15. ICC Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 16. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS IDS ODS VCC VCC
SU00095
Figure 17. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V
1998 May 01
17
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
EPROM CHARACTERISTICS
The 87C451 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87C451 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C451 manufactured by Philips Semiconductors. Table 4 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 18 and 19. Figure 20 shows the circuit configuration for normal program memory verification.
programmed, further programming of the code memory and encryption table is disabled. However, the other lock bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. Program Verification If lock bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 20. The other pins are held at the `Verify Code Data' levels indicated in Table 4. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 90H indicates 87C451
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in Figure 18. Note that the 87C451 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 18. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 4 are held at the `Program Code Data' levels indicated in Table 4. The ALE/PROG is pulsed low 25 times as shown in Figure 19. To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the lock bits, repeat the 25 pulse programming sequence using the `Pgm Lock Bit' levels. After one lock bit is
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 4, and which satisfies the timing specifications, is suitable.
Table 4. EPROM Programming Modes
MODE Read signature Program code data Verify code data Pgm encryption table Pgm lock bit 1 RST 1 1 1 1 1 PSEN 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* EA/VPP 1 VPP 1 VPP VPP P2.7 0 1 0 1 1 P2.6 0 0 0 0 1 P3.7 0 1 1 1 1 P3.6 0 1 1 0 1
Pgm lock bit 2 1 0 0* VPP 1 1 0 0 NOTES: 1. `0' = Valid low for that pin, `1' = valid high for that pin. 2. VPP = 12.75V 0.25V. 3. VCC = 5V 10% during programming and verification. * ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100s (10s) and high for a minimum of 10s.
TMTrademark phrase of Intel Corporation. 1998 May 01 18
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
+5V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87C451 P0 PGM DATA +12.75V 25 100s PULSES TO GROUND 0 1 0 A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00096
Figure 18. Programming Configuration
1 ALE/PROG: 0
25 PULSES
1 ALE/PROG: 0
10s MIN
100s+10
SU00018
Figure 19. PROG Waveform
+5V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87C451 P0 PGM DATA 1 1 0 0 ENABLE 0 A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00097
Figure 20. Program Verification
1998 May 01
19
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21C to +27C, VCC = 5V10%, VSS = 0V (See Figure 21) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL PARAMETER Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL s s s s MIN 12.5 MAX 13.0 50 6 UNIT V mA MHz
PROGRAMMING* P1.0-P1.7 P2.0-P2.4 ADDRESS
VERIFICATION* ADDRESS
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC 1 EA/VPP LOGIC 0
LOGIC 1
tEHSH
P2.7 ENABLE
tELQV
tEHQZ
SU00020
NOTE: * FOR PROGRAMMING VERIFICATION SEE FIGURE 18.
FOR VERIFICATION CONDITIONS SEE FIGURE 20.
Figure 21. EPROM Programming and Verification
1998 May 01
20
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
SOT188-3
1998 May 01
21
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 05-98 Document order number: 9397 75003857
Philips Semiconductors
1998 May 01 22

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